[EN] Real-time systems support a high variety of applications with hard real-time (HRT) constraints or soft (i.e. non-strict) real-time (SRT) constraints. Systems observing HRT constraints must guarantee execution time bounds for tasks with mandatory deadlines and usually do not require from complex processors. In contrast, applications with relaxed time constraints do not cause a system failure when missing a deadline, which just affects their quality of service. Examples of SRT applications are video encoding and decoding, which are becoming ubiquitous in our lifes. Unlike HRT applications, the computational requirements of SRT applications requires from complex microarchitectural techniques such as Simultaneous Multithreading (SMT). Unfortunately, unpredictability rises in SMT processors due to intra-core interference, which needs to be addressed in order to use SMT processors in real time systems. The goal of this work is to help make the system more predictable by means of thread to core allocation strategies, which in turn will help improve the performance. These strategies are mainly based on metrics concerning the L1 data cache bandwidth of the tasks, since it has been proved to be strongly related with the processor performance. Three strategies have been devised and evaluated. An important issue to carry out on this topic is the design of specific workloads to check the system behavior. To this end, a workload generator considering real-time parameters has been developed, which is also a key contribution of this work. In summary, this work makes two main contributions, i) we have devised and evaluated three thread-to-core allocation strategies for SRT systems and ii) we have designed and implemented an SRT workload generator. The experiments have been carried out on a system with an Intel Xeon E5645 processor. Experimental results show that the proposed L1 cache bandwidth aware Thread to Core Allocation policy allows performance enhancements. TFGM